Typically, the gate dielectric films of Metal Oxide Semiconductor (MOS) transistors are formed to be very thin, as the driving current of a MOS transistor may increase as the thickness of the gate dielectric film decreases. Thermal oxide films such as, for example, thermal silicon oxide films have been used as gate dielectric films since they typically do not adversely affect an underlying silicon substrate, and can be formed in a simple manner. However, silicon oxide films have a relatively low dielectric constant of, for example, about 3.9. Consequently, reductions in the thickness of a silicon oxide film used as a gate dielectric film may result in a higher gate leakage current. As a result, the degree to which the thickness of silicon oxide gate dielectric film may be reduced is restricted.
High dielectric constant or “high-k” dielectric films have also been used as gate dielectric films. While such high-k dielectric films are typically thicker than a silicon oxide film, they can still, in certain situations, improve device performance. There has been significant research into the use of high dielectric constant (high-k) dielectric films such as, for example, single metal oxide films made of hafnium oxide or zirconium oxide, metal silicate films made of hafnium silicate or zirconium silicate, and aluminate films made of hafnium aluminum oxide.
A pMOS device that includes a hafnium-based or zirconium-based dielectric film may exhibit a threshold voltage that is for example, 0.3-0.6V higher than the threshold voltage of a pMOS device that instead uses a silicon oxinitride (SiON) dielectric film. As the upper limit of the threshold voltage of a pMOS device which can be adjusted by channel engineering may be on the order of 0.1 to 0.2V, formation of a high-k dielectric film using conventional device fabrication processes may make it difficult to adjust a device threshold voltage to a desired level. In addition, when a polysilicon gate electrode is formed directly on a high-k dielectric film, gate depletion and/or degradation of the PBTI (Positive Bias Temperature Instability) characteristics of an nMOS device may result.